Introduction to Flip-Flops

Introduction

Despite the prevalence of microcontrollers to implement digital electronics, it’s useful to know how the fundamental building blocks work. This article will discuss one of these building blocks. The flip-flop and its different variants.

But before we begin, I’d like to clarify the difference between a latch and a flip-flop

Latch vs flip-flop

The difference is a latch is active all the time. I.e. any change in the input will change the output. Flip-flops are a clocked device. The output changes only when a certain input signal is triggered.

NOTE: A device that is Active High means that the inputs are held low and it takes a change to high to trigger the output. Active Low is the reverse. Inputs held high. A change to low (falling edge signal) is required to trigger the output

Overview

A flip flip usually has two inputs and two outputs. Two two outputs are the opposite of each other: When one is high, the other is low. One is labelled as Q, while the other is labelled as Q_bar. The BAR denotes the inverse, or opposite. So, if Q is high, Q_bar is low. If Q_bar is low, Q is high.

Flip flops are bistable, meaning they have two stable states. This is reflected in the outputs being either high or low. They can be used to store information. This represents a primitive form of memory.

The most basic Flip-Flop – the SR Flip-Flop

An SR flip-flop can be built from two NOR gates. See below:

NOTE: A NOR gate only outputs high when both inputs are low. If either input is high, the output is forced low

SR Latch circuit + NOR Truth Table

Set operation

SET operation
  1. We begin with the Initial State. Q = HIGH. In reality, at power-up both NOR outputs could momentarily go high, but one gate will win and settle first
  2. Q_BAR is held LOW until a HIGH pulse reaches SET pin
  3. Q goes LOW. Q_BAR goes HIGH
  4. Q is held LOW since both its inputs are HIGH
  5. The circuit is latched until RESET pin goes HIGH

RESET Operation

Reset operation
  1. We begin with the Initial State, which is state C for the SET operation
  2. A HIGH is delivered to RESET
  3. Q_BAR goes LOW
  4. Since two LOW inputs are in the upper NOR Gate, Q goes HIGH (This is state C)
  5. The circuit is in its other stable state

NOTE: For both SET and RESET operation, the SET and RESET pins are LOW in the latch’s stable state

One issue: A HIGH on SET and RESET causes unstable behavior, thus SR latches aren’t common. JK and D flip flops are preferred

An SR flip-flop with the addition of the Enable pin
SR NAND latch
SR NAND Latch with Enable Input

JK Flip Flop

To turn an SR flip-flop into a JK flip-flop, we add two AND gates. Each AND gate takes one of the Set/Reset inputs and a shared Enable/Clock line. Only when Enable is high will Set or Reset pulses propagate into the latch.

The outputs will only latch when a clock pulse (CP) is present. This behaviour is described as edge-triggered, since now the outputs flip on the rising or falling edge of the clock signal. A latch is level-triggered.

The operation is super simple.

If J=1, K=0, Flip Flop is SET. If J=0, K=1, Flip Flop is RESET

If J and K is tied together (J = K =1 ), the JK flip-flop will toggle state with every edge-change of the clock input.

This single characteristic allows us to use JK flip-flops as counters and dividers.

JK flip-flop

D flip-flop

A D flipflop is an SR flip-flop except instead of a Set and Reset pin at the input, there is a single Data pin.

Here’s the trick: whatever logic level is on D goes straight into the Set input, while the inverter feeds the opposite into Reset. So if D = 1, Set gets a 1 and Reset gets a 0. If D = 0, Set gets a 0 and Reset gets a 1. This ensures the invalid condition (S = R = 1) never happens.

It’s not helpful for the output to change every time the input does. An Enable pin at the input allows the device to remember the previous state of the D input. When Enable goes low again, the output stays latched, regardless of what D does afterward.

In the following circuit, a serial stream of 1s and 0s gets shifted into the next D flip-flop. After 4 pulses, a 4 bit value can be read.

Hey! We just built a SHIFT REGISTER

A shift register composed of D flip-flops

BONUS: NE555 as a latch

In the circuit below:

A negative pulse on trigger pin SETS the latch.

A positive pulse on threshold pin RESETS the latch.

NE555 connected as a SR flipflop

In Closing

I hope you have a better understanding of the different flip-flops that are available.

Summary